About this role
OpenAI has a vacancy for the role of RTL Design Engineer, Networking / NoC in San Francisco. This is a full-time position. The listing was posted on Nov 10, 2026. PakkiNaukri collects this listing from the employer's own posting and re-checks it — the employer's full description and the application itself are on the original listing, linked from this page.
From the employer's listing (short excerpt)
About the Team
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. The team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.
About the Role
We’re looking for an RTL Design Engineer to help design and develop next-generation AI accelerator silicon. In this role, you'll work across architecture, microarchitecture, and RTL implementation, translating complex system and performance requirements into efficient, scalable hardware designs.
You'll collaborate closely with silicon architects, hardware and software engineers, verification, and physical design teams to co-design hardware solutions optimized for demanding AI workloads. This is a hands-on engineering role with opportunities to influence architectural decisions, drive microarchitecture development, and own RTL design from early concept through implementation and integration.